Reference voltage regulator for eDRAM with VSS-sensing

ABSTRACT

A reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level includes an oscillator, a control block, a reference generator, a comparator, a pulse generator, a driver, and a reference voltage output, where the oscillator sends requests for sampling and correction to the control block between accesses of the eDRAM, the control block sends a pulse defining a time interval during which sampling and correction occurs to the pulse generator, the reference generator provides the reference level for comparison by the comparator with a sampling of the reference voltage output, the comparator decides if the reference voltage output requires correction and sends a correction request to the pulse generator if necessary, the pulse generator produces a correction pulse for the driver according to the correction request from the comparator, and the driver adjusts the reference voltage output during the correction pulse.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Provisional PatentApplication Ser. No. 61/218,644 filed on Jun. 19, 2009, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

This invention relates generally to reference voltage regulator forembedded dynamic random access memory (eDRAM) and, in particular, to thegeneration of a precise reference voltage level for eDRAM employingVSS-sensing with reference level.

BACKGROUND

A reference voltage at half-VDD is not sufficient enough to provide fastsensing and does not allow operating with a shorter cycle time. Fastsensing can be performed only if there is a large drain source voltage(Vds) for transistors in sense amplifier. The solution is to use VSS- orVDD-sensing, dependent on the type of memory cell access transistor. Forn-type access device VSS-sensing is used. To implement VSS-sensing, astable reference level close to VSS is required. There are twoconventional ways of generating the reference level: using an analogregulator or using reference cells. Each method has its own advantagesand drawbacks.

Analog push-pull voltage regulator requires relatively small area forgenerator. However, large voltage regulation (dV/dI) requires a largereservoir capacitor to compensate for the ripple of the reference level.The ripple of reference level can be minimized by improving the responseof the analog regulator, but it can be essentially done only byincreasing standby current. Another problem for analog regulator is togenerate stable levels close to VSS.

For conventional sensing schemes with reference cells, additional areain the array is needed and reference cells are usually different fromregular memory cells and thus more complicated. To activate referencecells, special levels different from the power supply voltage (>VDD) andthe ground voltage (<VSS) are required. Usually these levels are thesame as the levels for regular word-lines. This increases load forinternal generators that usually have low efficiency, and hence resultsin higher power consumption.

Accordingly, new schemes and methods are desired for the generation of aprecise reference voltage level for eDRAM.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates an example of a simplified schematic of a sensingscheme in eDRAM according to one aspect of the disclosure;

FIG. 2 illustrates an exemplary architecture of the reference voltage(VREF) regulator according to one aspect of this disclosure; and

FIG. 3 illustrates exemplary waveforms of the VREF regulator shown inFIG. 2.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent disclosure provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the disclosure, and do not limit the scope of the invention.

A reference voltage (VREF) regulator scheme for the generation of aprecise reference voltage level for eDRAM, employing VSS-sensing withreference level is provided. Using VSS-sensing allows operation at lowerVDD values and increasing current through the sense amplifiers. Areference generator is a precise ‘sample-and-correct’ type of voltagegenerator. In the present disclosure, a “sample/correct” VREF generatoris used to generate a reference level for eDRAM with VSS-sensing.Throughout the various views and illustrative embodiments of the presentdisclosure, like reference numbers are used to designate like elements.

FIG. 1 illustrates an example of a simplified schematic of a sensingscheme in eDRAM according one aspect of the disclosure. The VREFregulator 100 is connected to the row control circuit 200 through thereservoir capacitor 120 that further smoothes the output voltage fromthe VREF regulator. The row control circuit 200 is in turn connected tothe block of sense amplifiers 300.

The main component of the sensing scheme is the sense amplifiers in theblock 300. Bit-lines, i.e. BL and ZBL, are connected to multiple memorycells 302 and pre-charged to VSS. For every cycle, only one memory cell302 is selected, and the charge stored in a memory cell capacitor isshared with the initial charge on the bit-line. If logic ‘0’ is storedin the memory cell 302, the bit-line stays at the pre-charged level. Inthe case of logic ‘1’, the bit-line moves above VSS, by about ˜200 mV inone embodiment. A VREF regulator 100 generates reference level that isaround 100 mV. This voltage is applied to another bit-line that works asa reference for the sense amplifier. Just prior to sensing, the selectedbit-line is moved up by ˜200 mV or stays at VSS, and another referencebit-line is moved up by ˜100 mV.

Many sense amplifiers are grouped into one block 300 where all controllines are common. This block 300 is connected to a memory array segmentwith many bit-line pairs. During the sensing operation, all referencebit-lines in this segment, i.e. a half of all bit-lines, are moved tothe reference level. All control lines (e.g. VREFSA, RWL, ZRWL, SP, SSL)inside one block of sense amplifiers 300 are common for all senseamplifiers. Global bit-lines, i.e. GBL and ZGBL, provide an interfacebetween the sense amplifier and the periphery. Initially the global bitlines are also pre-charged to VSS, like local bit-lines BL and ZBL. TheSSL signal is high during the bit-line sensing and keeps column accessdevices closed. The node VREFSA in the local sense amplifiers plays adual role. When the word-lines are activated, node VREFSA is used toapply reference voltage to the reference bit-lines. In between word lineactivations, the VREFSA line stays at VSS, pre-charging all localbit-lines to ground.

Reference word-lines RWL and ZRWL are high during pre-charge and theVREFSA level is applied to both bit-lines. Before word-line activation,RWL or ZRWL (the line which does not correspond to the selectedbit-line) is pushed down to VSS, and the connection between selectedbit-line and VREFSA is off. After the word-line activation node VREFSAis connected to the reservoir capacitor 120, which is kept at VREFlevel, and all reference bit-lines in the memory array are pulled upfrom VSS to VREF level, selected bit-lines in memory array segment aredriven by memory cells 302 and moved above VREF level or stay at VSS.When the difference between BL and ZBL is big enough, the otherreference word-line is set low and at the same time SP node is pulled upamplifying an initial small differential signal. At the end of sensing,one bit line goes to VDD and the other stays at VSS.

FIG. 2 illustrates an exemplary architecture of the reference voltage(VREF) regulator according to one aspect of this disclosure. Thetemperature-controlled oscillator (TCO) 102 is an oscillator with outputfrequency proportional to temperature. TCO 102 is used together withFrequency Divider 104 to generate requests for level sampling/correctionbetween accesses. The control block 106 generates a pulse defining atime interval during which sampling/correction occurs. Requests can comefrom TCO 102 or from memory control logic 108 (in the dotted box toindicate outside of the VREF regulator 100).

The reference generator 110 provides a reference level for levelcomparison. The differential amplifier 112 amplifies the differencebetween the reference level and corrected output signal VREF. TheComparator 114 outputs a signal indicating if the level of output signalrequires correction. Based on the Comparator output, the pulse generator116 produces a short correction pulse for the driver 118, resetscomparator 114 and launches a new comparison cycle. The driver 118adjusts the output voltage during the pulse signal (PULL) duration fromthe pulse generator 116. The pulse width is wider if the correction isrequested by the memory control logic 108 (ACC_REQ). In one embodiment,the reservoir capacitor 120 can be about ˜1.5 nF capacitance,implemented with Metal Insulator Metal (MIM) decoupling capacitors.

During standby, TCO 102 sends requests to verify the VREF level, whichdegrades proportionally to the temperature because of leakage. Controlblock 106 generates a pulse that defines how long the“sampling/correction” cycle will last. Depending on how close VREF is tothe internal reference level REF, there could be from 5 to 20“sample/correct” attempts to minimize the difference between VREF andREF. Load current is much less during standby, which enables theregulator to operate in a more accurate mode and keep the VREF levelwith minimal ripples. Comparator 114 is included into the loop of pulsegenerator 116. Since internal delay in the comparator 114 is inverselyproportional to the difference of its inputs, the “sample/correct” rateis higher when the difference is bigger and is lower when VREF is closerto REF. This approach reduces over-pumping and ripples.

During access, memory control logic 108 sends level verificationrequests every access cycle. Usually this “sample/correct” cycle islonger than the access cycle. Thus, if there is a continuous access, theVREF generator 100 is always active. Moreover, time intervals when thedriver 118 is on are longer during an access than during a standby. Thissolution allows increasing load current during access. After anindividual access or the last in a series of accesses, a standbycorrection request is generated from control block 106 to verify, and ifrequired, correct the VREF level in a more accurate mode.

FIG. 3 illustrates exemplary waveforms of the VREF regulator shown inFIG. 2. During standby mode, the level verification requests (SBY_REQ)from TCO 102 through frequency divider 104 are shown as short pulses.These trigger the standby correction requests (SBY_CORR) from controlblock 106, which generates longer pulses defining time intervals duringwhich sampling/correction occurs. The result is the multiple PULL signal(short pulses) generated from pulse generator 116, which corrects theVREF output using the driver 118. In this embodiment, the VREF referencevoltage (REF) is shown to be ˜130 mV above VSS.

During access, the level verification requests (ACC_REQ) for everyaccess cycle sent from the memory control logic 108 to the control block106 are shown as short pulses. These trigger the access correctionrequests (ACC_CORR) from control block 106, which generates longerpulses defining time intervals during which sampling/correction occurs,longer than the standby correction requests (SBY_CORR). Thus, becausethere is a continuous access during the access mode shown in FIG. 3,ACC_CORR is shown as a long continuous pulse during access instead ofmultiple pulses. The result is the multiple PULL signal (longer pulsescompared to standby mode) generated from pulse generator 116, whichcorrects the VREF output using the driver 118. In this embodiment, theVREF output voltage is shown to be within ˜10 mV of variation centeredat the reference voltage (REF). After the accesses, the post-accesscorrection is triggered by control block 106 that generates a standbycorrection request (SBY_CORR). This results in multiple PULL signal(short pulses) from pulse generator 116, which corrects the VREF outputusing the driver 118.

The reference level VREF has to have minimal process deviations andripple during access in order to maximize the window for signal from thememory cell 302. To achieve this, various embodiments according to oneaspect of this disclosure can have the following features: (1) powerdomain is the same as eDRAM domain, (2) high “sample/correct” rate (e.g.˜1 GHz), (3) when level needs to be corrected, correction is done bysmall steps (e.g. a few mV), yielding a more smooth reference level, (3)adaptive loop with the comparator 114 as part of sampling clockgeneration loop (the closer the reference level to the target, the lowerthe sampling rate; the next sampling is delayed until the requiredcorrection is fully finished, or is done immediately if correction isnot required), (4) variable VREF step (small steps during standbyoperation and large steps during active operation to minimize overshootduring level correction), and (5) small arrays of Metal Insulator Metal(MIM) decoupling capacitors are combined into one reservoir capacitorthat allows to use chip area more effectively because of highMIM-capacitance per area.

The advantageous features of this disclosure include lower powerconsumption than prior art approaches (e.g. push-pull amplifier)especially in standby mode (e.g. 32 μA instead of 200-300 μA for atypical 4 MBit in one embodiment), fast reaction time, smaller area(although area may be dominated by reservoir capacitor), betteraccuracy, and the ability to generate well controlled voltages close toground (˜100 mV typical), where the pull-down of a conventionalamplifier would fall out of saturation. Using VSS-sensing to allowoperation under lower VDD values and increasing current through senseamplifier. The ‘sample-and-correct’ scheme of the voltage regulator ineDRAM provides an adaptive correction method that has a highersample/correct rate when the difference between a target referencevoltage and the actual output voltage is bigger.

In particular, in one embodiment using a VSS-sensing scheme for eDRAMmemory array with N-type memory array has a few advantages: (1) itallows operations with lower VDD without performance degradation, andall bit-lines are pre-charged to VSS and the current in sense amplifierduring sensing is maximized, (2) differential signal is amplified with aP-type cross-coupled transistor pair, that has less offset than anN-type cross-coupled pair, (3) smaller offset makes possible to use asingle direct reference level for many sense amplifiers grouped into alarge array, and (4) bigger Vds in memory cell speeds up charge sharingduring bit line split.

A skilled person in the art will appreciate that there can be manyembodiment variations of this disclosure. Although the advantages of thepresent disclosure have been described in detail, it should beunderstood that various changes, substitutions and alterations can bemade herein without departing from the spirit and scope of theinvention. Moreover, the scope of the present application is notintended to be limited to the particular embodiments of the process,machine, manufacture, and composition of matter, means, methods andsteps described in the specification. As one of ordinary skill in theart will readily appreciate from the disclosure, processes, machines,manufacture, compositions of matter, means, methods, or steps, presentlyexisting or later to be developed, that perform substantially the samefunction or achieve substantially the same result as the correspondingembodiments described herein may be utilized according to the presentdisclosure.

1. A reference voltage regulator for an embedded dynamic random accessmemory (eDRAM) employing VSS-sensing with a reference level, comprising:an oscillator; a control block; a reference generator; a comparator; apulse generator; a driver; and a reference voltage output; wherein theoscillator is configured to send requests for sampling and correction tothe control block between accesses of the eDRAM, the control block isconfigured to send a pulse defining a time interval during whichsampling and correction occurs to the pulse generator, the referencegenerator is configured to provide the reference level for comparison bythe comparator with a sampling of the reference voltage output, thecomparator is configured to decide if the reference voltage outputrequires correction and based on the decision send a correction requestto the pulse generator, the pulse generator is configured to produce acorrection pulse for the driver according to the correction request fromthe comparator, and the driver is configured to adjust the referencevoltage output during the correction pulse.
 2. The reference voltageregulator of claim 1, wherein the reference voltage regulator isconfigured to adjust a rate for sampling and correction so that the rateis higher when a difference between the reference level and thereference voltage output is larger.
 3. The reference voltage regulatorof claim 2, wherein the reference voltage regulator is configured toadjust the rate by using an internal delay in the comparator that isinversely proportional to the difference between the reference level andthe reference voltage output.
 4. The reference voltage regulator ofclaim 1, wherein the reference voltage regulator is configured to alsosend the requests for sampling and correction from a memory controllogic in the eDRAM to the control block for an access.
 5. The referencevoltage regulator of claim 4, wherein the pulse generator is configuredto produce correction pulses with a width that is wider when the memorycontrol logic sends the requests for sampling and correction.
 6. Thereference voltage regulator of claim 4, wherein the control block isconfigured to start a new comparison cycle to correct the referencevoltage output after the access.
 7. The reference voltage regulator ofclaim 1, wherein a differential amplifier is configured to amplify adifference between the reference level and the reference voltage outputand send the amplified difference to the comparator.
 8. The referencevoltage regulator of claim 1, wherein the pulse generator is configuredto reset the comparator and launch a new comparison cycle when the pulsegenerator produces the correction pulse.
 9. The reference voltageregulator of claim 1, wherein a reservoir capacitor is coupled to thereference voltage output.
 10. The reference voltage regulator of claim9, wherein the reservoir capacitor is implemented with Metal InsulatorMetal (MIM) capacitors.
 11. The reference voltage regulator of claim 1,wherein the oscillator is a temperature controlled oscillator (TCO). 12.The reference voltage regulator of claim 11, wherein the referencevoltage regulator is configured to send requests for sampling andcorrection from the oscillator through a frequency divider before therequests are sent to the control block.
 13. A reference voltageregulator for an embedded dynamic random access memory (eDRAM) employingVSS-sensing with a reference level, comprising: an oscillator; afrequency divider; a control block; a reference generator; adifferential amplifier; a comparator; a pulse generator; a driver; and areference voltage output; wherein the oscillator is coupled to afrequency divider, the frequency divider is configured to send requestsfor sampling and correction to the control block between accesses of theeDRAM, the control block is configured to send a pulse defining a timeinterval during which sampling and correction occurs to the pulsegenerator, the reference generator is configured to provide thereference level for comparison by the comparator with a sampling of thereference voltage output, the differential amplifier is configured toamplify a difference between the reference level and the referencevoltage output before the difference is sent to the comparator, thecomparator is configured to decide if the reference voltage outputrequires correction and send a correction request to the pulsegenerator, the pulse generator is configured to produce a correctionpulse for the driver according to the correction request from thecomparator, the driver is configured to adjust the reference voltageoutput during a correction pulse, and the reference voltage regulator isconfigured to adjust a rate for sampling and correction to be higherwhen the difference between the reference level and the referencevoltage output is larger.
 14. The reference voltage regulator of claim13, wherein the reference voltage regulator is configured to adjust therate by using an internal delay in the comparator that is inverselyproportional to the difference of the reference level and the referencevoltage output.
 15. The reference voltage regulator of claim 13, whereinreference voltage regulator is configured to also send the requests forsampling and correction from a memory control logic in the eDRAM to thecontrol block for an access.
 16. The reference voltage regulator ofclaim 15, wherein the pulse generator is configured to produce thecorrection pulse with a width that is wider when the memory controllogic sends the requests for sampling and correction.
 17. The referencevoltage regulator of claim 15, wherein the control block is configuredto start a new comparison cycle to correct the reference voltage outputafter the access.
 18. The reference voltage regulator of claim 13,wherein the pulse generator is configured to reset the comparator andlaunch a new comparison cycle when the pulse generator produces thecorrection pulse.
 19. A reference voltage regulator for an embeddeddynamic random access memory (eDRAM) employing VSS-sensing with areference level, comprising: a temperature controlled oscillator (TCO);a frequency divider; a control block; a reference generator; adifferential amplifier; a comparator; a pulse generator; a driver; and areference voltage output; wherein the TCO is coupled to a frequencydivider, the frequency divider is configured to send requests forsampling and correction to the control block between accesses of theeDRAM, the control block is configured to send a pulse defining a timeinterval during which sampling and correction occurs to the pulsegenerator, the reference generator is configured to provide thereference level for comparison by the comparator with a sampling of thereference voltage output, a differential amplifier is configured toamplify a difference between the reference level and the referencevoltage output and send the amplified a difference to the comparator,the comparator is configured to decide if the reference voltage outputrequires correction and send a correction request to the pulse generatorthe pulse generator is configured to produce a correction pulse for thedriver based on the correction request from the comparator, the driveris configured to adjust the reference voltage output during thecorrection pulse, and the reference voltage regulator is configured toadjust a rate for sampling and correction to be higher when thedifference between the reference level and the reference voltage outputis larger.
 20. The reference voltage regulator of claim 19, wherein thereference voltage regulator is configured to also send the requests forsampling and correction from a memory control logic in the eDRAM for anaccess, pulse generator is configured to produce correction pulses witha width that is wider when the memory control logic sends the requestsfor sampling and correction, and the control block is configured tostart a new comparison cycle to correct the reference voltage outputafter the access.